1. Field of the Invention
The present invention relates to a logic circuit device, and particularly to a logic circuit device provided with a circuit for increasing a switching speed.
2. Description of the Prior Art
FIG. 4 is a circuit diagram illustrating essential structures of a BiCMOS logic circuit disclosed in the Japanese Laid-Open Patent Publication No. 59-11034. In the figure, the BiCMOS logic circuit is so constructed that a signal inputted through a signal input terminal 1 is inverted, and then is outputted from a signal output terminal 2. This BiCMOS logic circuit consists of a P-channel MOS transistor 3 (will be called as "PMOS transistor"), a N-channel MOS transistor 4 (will be called as "NMOS transistor"), npn bipolar transistors 5 and 6, and resistors 7 and 8. The PMOS transistor 3 and the NMOS transistor 4 are interposed in series between a power source V.sub.cc and a ground GND to form a so-called CMOS inverter. The resistor 7 is disposed between the PMOS transistor 3 and the NMOS transistor 4, and the resistor 8 is disposed between the NMOS transistor 4 and the ground GND. The gates of the PMOS transistor 3 and the NMOS transistor 4 are connected to the signal input terminal 1. A connection between the resistor 7 and the NMOS transistor 4 is connected to the signal output terminal 2. The bipolar transistor 5 has a collector connected to the power source V.sub.cc, an emitter connected to the signal output terminal 2, and a base connected to a connection between the PMOS transistor 3 and the resistor 7. The bipolar transistor 6 has a collector connected to the signal output terminal 2, an emitter connected to the ground GND, and a base connected to a connection between the NMOS transistor 4 and the resistor 8.
FIG. 5 is a cross section illustrating a part of laminated structures of a semiconductor substrate and the BiCMOS logic circuit shown in FIG. 4. In FIG. 5, there are formed on a surface layer of a P-type semiconductor substrate 10, a N.sup.+ impurity diffusion layer 4d forming a drain of the NMOS transistor 4 in FIG. 4 and a N.sup.+ impurity diffusion layer 4s forming a source thereof with a predetermined space therebetween. A gate electrode 4g is formed on the semiconductor substrate 10 with an insulator film therebetween and is located in an area between these impurity diffusion layers 4d and 4s. There are also formed on the surface layer of the semiconductor substrate 10 a N.sup.+ impurity diffusion layer 6c forming the collector of the bipolar transistor 6 in FIG. 4, a P.sup.+ impurity diffusion layer 6b forming the base thereof and a N.sup.+ impurity diffusion layer 6e forming the emitter thereof. Further, a P.sup.+ impurity diffusion layer 80 which forms the resistor 8 in FIG. 4 is formed on the surface layer of the semiconductor substrate 10. It should be noted that a thick insulator film 11 is provided to separate the bipolar transistor 6 consisting of the impurity diffusion layers 6c, 6b and 6e and the resistor 8 consisting of the impurity diffusion layer 80.
FIG. 6 is a voltage waveform diagram illustrating a manner in which an output voltage V.sub.out at the signal output terminal 2 varies in accordance with the variation of an input voltage V.sub.in at the signal input terminal 1 in the BiCMOS logic circuit shown in FIG. 4. Now, operations of the conventional logic circuit shown in FIG. 4 will be described with reference to FIG. 6.
Before a switching operation of the logic circuit, the input voltage V.sub.in at the signal input terminal 1 is in a "L" level. Therefore, the NMOS transistor 4 is turned off, and the PMOS transistor 3 is turned on. Accordingly, the signal output terminal 2 is connected through the resistor 7 and the PMOS transistor 3 to the power source V.sub.cc, and thus the output voltage V.sub.out at the signal output terminal 2 is in a "H" level.
When the input voltage V.sub.in at the signal input terminal 1 varies to the "H" level, the NMOS transistor 4 is turned on, and the PMOS transistor 3 is turned off. As a result, a charge which has been charged in a load capacity (not shown) connected to the signal output terminal 2 is discharged through the NMOS transistor 4 and the resistor 8 to the ground GND (period t1).
The above discharged current flows through the resistor 8 to the ground GND, and also forms a base current of the bipolar transistor 6 to turn on it. As a result, owing to a high current driving ability of the bipolar transistor 6, the charge in the signal output terminal 2 is rapidly discharged (period t2).
When the potential at the signal output terminal 2 decreases to some extent, the end voltages of the resistor 8 have a value smaller than a voltage between the base and emitter required for turning on the bipolar transistor 6, so that the bipolar transistor 6 shifts to an off state. Thereafter, a residual charge in the signal output terminal 2 is discharged through the NMOS transistor 4 and the resistor 8 (period t3). The charge accumulated in the base of the bipolar transistor 6 is also discharged through the resistor 8 in this period t3.
As apparent from the above description, the resistor 8 in the logic circuit shown in FIG. 4 performs two functions in the switching operation. That is; the resistor 8 functions to supply the current from the NMOS transistor 4 to the base of the bipolar transistor 6 at an initial stage in the switching operation, and also functions to discharge the residual charge in the signal output terminal 2 and the base charge in the bipolar transistor 6 at a later stage in the switching operation. With respect to the former function, a higher resistance of the resistor 8 is preferable in view of a higher speed of the switching operation, because the higher resistance of the resistor 8 can supply a larger base current for the bipolar transistor 6. On the other hand, in view of the latter function, the lower resistance of the resistor 8 is preferable, because the lower resistance can reduce the discharging time of the residual charge in the signal output terminal 2 and the base charge of the bipolar transistor 6.
As described above, the resistance of the resistor 8 is preferable to be high at the initial stage in the switching operation and to be low at the later stage. Therefore, the above points have been totally taken into consideration in the design of the conventional circuit shown in FIG. 4, in which the resistor 8 has a resistance of a pre-calculated value which can achieve the highest speed of the switching operation on an average. However, even if the resistor 8 is set to have such resistance, the resistance can not always be of an optimum value for the every operating condition of the circuit, because the resistor 8 is a fixed resistor. Accordingly, the conventional logic circuit shown in FIG. 4 still has a problem concerning a speed of the switching operation.
As shown in FIG. 5, it is required in the conventional BiCMOS logic circuit to separate a formation region for the bipolar transistor 6 and that for the resistor 8 from each other, which disadvantageously increases a circuit area. This is due to a fact that the resistance of the resistor 8 is strictly required to be of the optimum value obtained from the calculation as described above, and thus it is necessary to prevent variation of the resistance of the resistor 8, which may be caused by an influence on the P.sup.+ impurity layer 80 by the impurity diffusion region forming the bipolar transistor.